1. Field of the Invention
The present invention relates to a semiconductor package and, more particularly, to a three-dimensional package that combines a plurality of chip scale packages (CSPs) stacked using an anisotropic conductive film interposed between CSPs and a method of manufacturing such packages.
2. Description of the Related Art
As the electronic industry pushes for smaller, lighter, faster, more versatile, higher-performance, more reliable, and cheaper products, package assembly technology becomes more important to achieve these design goals. A ball grid array (BGA) package is one solution that tends to offer reduced assembly area on a mother board and improved electrical characteristics when compared with other common plastic packages.
In contrast to conventional plastic packages, BGA packages typically use a printed circuit board (PCB) instead of a lead frame. The BGA package has an array of solder balls formed on the bottom surface of the printed circuit board and can provide high density mounting on a mother board. BGAs, however, limit the degree to which the size of the PCB can be decreased. Because the semiconductor chip is attached to a portion of PCB on which circuit wires are not formed, the PCB is necessarily larger than the semiconductor chip. Chip scale packages (CSPs) have been introduced to address this limitation.
Various types of CSPs have been introduced by companies in the U.S., Japan, and Korea and others are being developed. A representative example of a CSP is a BGA package utilizing a tape circuit board in which a circuit pattern is formed on a flexible polyimide tape. Beam lead bonding or wire bonding are generally used to establish electrical connections between the tape circuit board and the semiconductor chip.
Another technology used for reducing package size is the three-dimensional stacking of a plurality of semiconductor chips and/or packages. A package incorporating this three-dimensional packaging is usually called a stack package.
A stack package that includes a plurality of normal semiconductor packages in one package tends to reduce the failure rate because the stack package is constructed only from semiconductor packages that have already passed a reliability and/or functionality test. However, the thickness of the stack package increases in direct proportion to the number of semiconductor packages stacked. A stack package with a plurality of semiconductor chips (also called a ‘stacked chip package’) can provide a reduced package thickness, but also tends to increase the risk of high failure rate since the functionality of each of the included semiconductor chips is not verified prior to its inclusion in the package. In light of these problems, stack packages including a plurality of CSPs are preferred as they typically provide a combination of the lower failure rate associated with stack packages of normal semiconductor packages and the reduced thickness of the stacked chip package.
FIG. 1 shows a conventional stack package 200 including two CSPs 110a and 110b. As illustrated in FIG. 1, the CSP 110a, the lower CSP, and the CSP 110b, the upper CSP, are arranged in a stacked configuration. When the conventional stack package 200 has three or more CSPs, additional intermediate CSPs (not shown) are interposed between the uppermost CSP and lowermost CSP.
As illustrated in FIG. 1, the lower and upper CSPs 110a, 110b each includes a semiconductor chip 120 and a circuit board 130. The semiconductor chip 120 is mounted on a top surface of the circuit board 130, and solder balls 170 are provided on peripheral regions, i.e., outside the edges of the semiconductor chip, of a bottom surface of the circuit board 130. In order to allow three-dimensional stacking of the CSPs 110a and 110b, the height of solder balls 170 will typically be greater than the height of the semiconductor chip 120 to maintain separation of the semiconductor chip and the circuit board.
The conventional stack package 200 is manufactured by directly attaching the solder balls 170 of the upper CSP 110b to the top surface of the circuit board 130 of the lower CSP 110a. To accomplish this, a solder reflow process (hereinafter referred to as a “reflow process”) is performed after the upper CSP 110b is mounted so that the solder balls 170 are aligned with corresponding structures provided on the top surface of the circuit board 130 of the lower CSP 110a. 
During the reflow process(es) applied to the conventional package during the three-dimensional stacking of a plurality of CSPs, thermal stress exerted on the CSPs may result in mechanical failures such as warpage of the package. Because conventional CSPs are relatively thin, they tend to be more susceptible to thermal stress than larger packages. Further, the multiple reflow processes carried out when forming solder balls on a CSP and when forming a stack package increases the possibility of warpage of the included CSPs. The warpage of the CSPs may, in turn, degrade solder attachment reliability between adjacent CSPs due to variation in height of solder balls.
In particular, an unacceptable degree of misalignment of the solder balls detected during the manufacture of a stack package may prompt a repair or rework process that will include at least one additional reflow process. The thermal stresses exerted during these “repair” reflow process(es) will tend to increase the possibility of warping one or more of the CSPs.
Furthermore, when CSPs having misaligned solder balls are separated during a repair process, the solder balls attaching the adjacent CSPs being separated may separate incompletely, particularly where the solder balls of an upper CSP have been solidly attached to a circuit board of a lower CSP using a reflow process. Because a CSP with one or more defective solder balls will usually be rejected, this rework or repair process will also tend to reduce the manufacturing yields. In addition, using a CSP that has suffered minor, but undetected, damage may avoid being rejected and may degrade the reliability of a manufactured stack package incorporating the damaged CSP.